Hi, Sebastian,
Thank you very much for your help. From the result you sent, the biggest
performance degradation is between step 4 and step 5. In that step, one
more register is saved before and restored after encryption/decryption.
So I think the reason maybe the read/write port throughput of CPU.
I changed the patches to group the read or write together instead of
interleaving. Can you help me to test these new patches? The new patches
is attached with the mail.
Best Regards,
Huang Ying
On Thu, 2008-04-24 at 00:32 +0200, Sebastian Siewior wrote: